A DRAM is a device formed by combination of many memory cells composed of a transistor and a capacitor. Recently, DRAMs are being integrated in higher density in response to demands for larger memory capacity. Therefore, techniques for reducing a memory cell size to integrate more memory cells in a confined space have been required.
FIG. 1 illustrates a conventional DRAM cell structure. As shown in FIG. 1, a conventional DRAM cell structure includes a transistor device formed horizontally on a silicon substrate, and a capacitor device having a plate electrode and a storage node electrode formed on a stacked layer over the transistor device.
However, the conventional horizontal DRAM cell structure shown in FIG. 1 has drawbacks. First, integration density is limited due to word-line size and length. Second, it is difficult to secure a large enough size of the capacitor for sufficient capacitance.